The present invention relates to a semiconductor memory and, more particularly, to a large-capacity dynamic RAM (random access memory) and related techniques for making the memory larger, faster, more integrated and less expensive than before.
Data line dividing (i.e., layering) techniques are disclosed illustratively in U.S. Pat. Nos. 4,590,588, 5,301,142, 5,297,102 and 5,404,338 as well as in Japanese Patent Laid-Open No. Hei 5-54634. Word line layering techniques are disclosed illustratively in U.S. Pat. Nos. 5,140,550 and 5,282,175, and in Japanese Patents Laid-Open Nos. Hei 1-245489 and Hei 2-158995. Japanese Patent Laid-Open No. Hei 2-18785 discloses techniques for installing amplifier MOSFETs between complementary data lines and complementary common data lines.
There exist semiconductor memories such as the dynamic RAM having as its basic components memory arrays each including a plurality of word lines and bit lines intersecting orthogonally and a large number of dynamic memory cells located in lattice fashion at the intersection points between the intersecting word and bit lines. In recent years, dynamic RAMs have been getting larger in capacity and more integrated in scale at rapid pace. Varieties of techniques are being disclosed to accelerate the trend.
For instance, the so-called layered word line structure is proposed in “ISSCC (International Solid-State Circuits Conference) '93 Digest of Technical Papers, Session 3” (Feb. 24, 1993; pp. 50-51). The proposed structure (called the first conventional example hereunder) involves arranging main word lines in parallel with sub-word lines, the pitch between the main word lines being made an integer multiple of that between the sub-word lines. The arrangement is intended to enlarge the wiring pitch of a metal wiring layer constituting the main word lines and thereby to enhance the degree of circuit integration of dynamic RAMS. In another example (called a second conventional example), Japanese Patent Publication No. Hei 4-59712 discloses the so-called layered I/O structure in which designated bit lines are connected to main common I/O lines by way of relatively short sub-common I/O lines. The structure is intended to alleviate the loads on sense amplifiers and thereby speed up read operations of dynamic RAMs.
In addition, U.S. Pat. No. 5,274,595 issued on Dec. 28, 1993 discloses a method (a third conventional example) for connecting sub-common I/O lines to main common I/O lines via a plurality of summing direct sense type sub-amplifiers, the sub-amplifiers being located where word line shunts and sense amplifiers intersect. The disclosed method is intended to minimize the increase in the layout area for accommodating a plurality of sub-amplifiers while speeding up the operation of dynamic RAMs.